On 06/05/2013 01:48 PM, Gullik Webjörn wrote:
The problem is that this has to avoid overlap in any of /number-of-carriers/ * /number-of-symbols/ cases, where each is a different phase modulation. Now, this seems intractable to an innumerate person like me (at least by the standards of Rowe et al) but that doesn't mean you should not think about it.Enough rambling, the point was that all these carriers "added up" causing high PAPR , the solution was to "randomize" the PHASE, and minimize "adding up". Perhaps something similar could be done here, i.e. each carrier has a certain phase offset that is constant, but different from all carriers?
I came up with one. Invert the clock carrier phase when there's a pernicious combination. The receive PLL wil stay locked if there's a low rate of this happening.
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