Hi Glen,

Thank you very much for your input.  I will carefully consider each of 
your suggested changes.

At this stage I am feeling conservative - for the Betas I want to 
minimise risk as any bugs we introduce from changes will results in 100 
repairs.

So I'm inclined to separate mods to:

(i) those that are low risk to add on the Betas
(ii) possible improvements we can try out in a later prototype stage.

So the 100uH inductor kick is a good example of something we need to be 
very careful with.  Might be best to replace that with a bead, as 
currently tested in the prototype.  We could always increase R21 to form 
a RC filter blocking switcher hash from re-radiating.

Re (4) I could hear reduced switcher noise on the speaker output when I 
tacked an electrolytic across C25, which was initially specified as a 
ceramic (not sure what material however).  Had assumed a tant would be 
just as good?

Cheers,

David

On 29/09/14 09:00, glen english wrote:
> I have some schematic comments
>
> Critical :
>
> 1)
> Try to avoid connecting input pins of the CPU to Vdd. This is bad !
>
> IE PTT, SELECT, BACK (SW1,2,4)
>
> A latch up condition would mean destruction of the chip.
>
> If there needs to be input pins tied to Vdd, tie them through a low
> value resistor, like 470 ohms . NOT direct to supply.
>
> Improvements :
>
> 2) A stubber should be present on the switched mode supplu switching
> node. This will substantially reduce the ringing rubbish
> Jn C27/L2
>
> 3) A 2 ohm resistor in series with C26 will also reduce radiated rubbish
>
>
> 4) A ceramic cap (X7R, X5R, X7S) would be a MUCH better choice for C25,
> C29, C28  in the power supply.
> Tantalums will under perform here . Eliminate C1.
>
> A bulk electrolytic may be a good choice on the input to reduce ringing
> and reduce Q of the equiv circuit. Put there where C1 was.
>
>
> 5) The 100uH inductor is a loaded gun....it may kick 2x or more voltage
> into the switched mode chip at power up- suggest the electrolytic be
> across C1, and/or a zener to clamp to spike
>
>
> comments
>
> 4) VREF+ may have too high a value resistor (R10) - successive ADC
> operations will deplete the reference stored in the C10 cap and generate
> errors. IE the first conversion is good, but subsequent conversions
> will show a higher conversion because The VREF+  will sag.
> This may not be a problem in this application- but it is if you are
> trying accurately to measure say a battery voltage.
>
> 5) Rather than the half rail supply splitting resistors everywhere for
> the op amp Vhalf-rail (VHR) , why not drop a opamp down and provide this
> voltage. this would eliminate 2 large  capacitors and 2 resistors.
>
>
>
> On 29/09/2014 6:28 AM, David Rowe wrote:
>> Yes I linked to the prototype schematic, as that was what I was
>> debugging.  The beta schematic is being worked on now.
>>
>> On 29/09/14 00:53, Steve wrote:
>>> The articles schematic link is old, I think this is the newest one:
>>>
>>> http://sourceforge.net/p/freetel/code/HEAD/tree/smartmic/SM1000-C/SCH-SM1000-C.pdf
>>>
>>>
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