Hello Gregory,

Thanks for reminding me about the low PAPR/FEC idea, yes I think I have 
a paper on that somewhere too.

Rateless modulation sounds cool ... so many things to look into!

Yes, we would need to test the CPU load for LDPC decoding, especially on 
the STM32F4.

Cheers,

David

On 24/11/14 18:04, Gregory Maxwell wrote:
> On Mon, Nov 24, 2014 at 6:30 AM, David Rowe <da...@rowetel.com> wrote:
>> Here's the scoop:
>>
>>     http://www.rowetel.com/blog/?p=3700
>
> Very nice results.
>
>
> You might be interested in some of the interesting things people are
> doing with rateless coded modulation,
> http://nms.csail.mit.edu/spinal/  ... mostly applicable to data rates,
> SNRs, and latencies which are outside of your target,  the notion of
> encoding enhancement bits always in higher order modulation, for use
> when the channel happens to actually have more margin sounds like it
> would fit nicely with the goal you state for auxiliary carriers.
>
>> Given the relatively short block length, is an LDPC code the best choice?
>
> Well, the bigger consideration might be the available decoder
> computational resources. Since there really is no super fast lower
> quality decode of the LDPC possible.
>
> I think I'd commented before that a half rate golay code with tightly
> packed OFDM QPSK carriers can give a worst case PAPR of 3dB (there are
> quite a few papers on this now if you goggle; though most of the
> recent papers are about extending it to higher order modulations) ...
> so there is a least one approach where the FEC can be structured to
> directly reduce the original signal PAPR, effectively getting most of
> the power overhead the code adds back.  So there may be some to gain
> in exploring how the FEC interacts with PAPR.
>
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