On the PC, changing from single to double for large datasets starts to really hurt because the effective doubling of the dataset space starts to hurt you on cache misses ... Not such an issue on non cache single-cycle access SRAM type architectures. (though a 64 bit fetch from a 32 bit wide SRAM memory is GOING to cost something).
the M_PI is a good point though.... easily overlooked as doubling everything.... g On 20/06/2016 8:24 PM, Maxime Guyon wrote: > I'm agree with glen english for the float parts, use only double where > it's necessary... > > Also Bruce, it seem that many CPU which can handle double operation > can also handle simultaneous single float operation which will not > reduce the speed... > > Saving cycle is important on embedded platform and even if MIPS are > cheap, energy and power is not the same story in embedded system. > Smaller CPU often provide the lowest standby power consumption and so > a longer working time on battery powered device. > > Regards. ------------------------------------------------------------------------------ Attend Shape: An AT&T Tech Expo July 15-16. Meet us at AT&T Park in San Francisco, CA to explore cutting-edge tech and listen to tech luminaries present their vision of the future. This family event has something for everyone, including kids. Get more information and register today. http://sdm.link/attshape _______________________________________________ Freetel-codec2 mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/freetel-codec2
