Owen wrote: >> My guess is any realistic solution will be hybrid, combining the >> features of all these large scale architectures. >> By designing circuits to do special purpose compute tasks, the lengths of wires can be reduced (and thus their diameter) and this is ultimately the limiting factor on serial performance and circuit density. In practice, designing these circuits is hard to automate and optimize (even with FPGAs) and even relatively general hybird computing approaches like the Cell broadband engine still require quite a bit of programming finesse (e.g. prefetching and keen awareness of memory access patterns, etc.)
Of course, at some point the wire diameters can get no smaller, and we have to look to programming approaches to find parallelism. One software technology that looks promising to me is software transactional memory: http://en.wikipedia.org/wiki/Software_transactional_memory Apparently Sun is working on hardware support for it.. http://www.theregister.co.uk/2007/08/21/sun_transactional_memory_rock/ ============================================================ FRIAM Applied Complexity Group listserv Meets Fridays 9a-11:30 at cafe at St. John's College lectures, archives, unsubscribe, maps at http://www.friam.org
