------- Comment #3 from steven at gcc dot gnu dot org  2009-06-20 07:23 -------
Output from ./cc1 -march=armv5te -mthumb -Os PR40499.c -dAP:

        .file   "PR40499.c"
        .text
        .align  1
        .global dual_feasible
        .code   16
        .thumb_func
        .type   dual_feasible, %function
dual_feasible:
        @ basic block 2
@(insn 42 37 43 PR40499.c:11 (set (reg/v/f:SI 2 r2 [orig:169 stop ] [169])
@        (mem/s/f:SI (plus:SI (reg/v/f:SI 0 r0 [orig:172 net ] [172])
@                (const_int 4 [0x4])) [3 <variable>.stop_arcs+0 S4 A32])) 168
{*thumb1_movsi_insn} (nil))
@ 0x0000
        ldr     r2, [r0, #4]    @ 42    *thumb1_movsi_insn/7    [length = 2]
@(insn 43 42 108 PR40499.c:13 (set (reg/v/f:SI 3 r3 [orig:167 arc ] [167])
@        (mem/s/f:SI (reg/v/f:SI 0 r0 [orig:172 net ] [172]) [3
<variable>.arcs+0 S4 A32])) 168 {*thumb1_movsi_insn} (expr_list:REG_DEAD
(reg/v/f:SI 0 r0 [orig:172 net ] [172])
@        (nil)))
@ 0x0002
        ldr     r3, [r0]        @ 43    *thumb1_movsi_insn/7    [length = 2]
@(jump_insn 108 43 109 PR40499.c:13 (set (pc)
@        (label_ref 51)) 243 {*thumb_jump} (nil))
@ 0x0004
        b       .L2     @ 108   *thumb_jump     [length = 2]
.L4:
        @ basic block 3
@(insn 47 46 48 PR40499.c:15 (set (reg:SI 1 r1 [173])
@        (mem:SI (reg/v/f:SI 3 r3 [orig:167 arc ] [167]) [4 S4 A32])) 168
{*thumb1_movsi_insn} (expr_list:REG_EQUIV (mem:SI (reg/v/f:SI 3 r3 [orig:167
arc ] [167]) [4 S4 A32])
@        (nil)))
@ 0x0006
        ldr     r1, [r3]        @ 47    *thumb1_movsi_insn/7    [length = 2]
@(jump_insn 48 47 49 PR40499.c:15 (set (pc)
@        (if_then_else (le (reg:SI 1 r1 [173])
@                (const_int 7 [0x7]))
@            (label_ref:SI 70)
@            (pc))) 200 {*cbranchsi4_insn} (expr_list:REG_DEAD (reg:SI 1 r1
[173])
@        (expr_list:REG_BR_PROB (const_int 450 [0x1c2])
@            (nil))))
@ 0x0008
        cmp     r1, #7  @ 48    *cbranchsi4_insn/1      [length = 4]
        ble     .L5
        @ basic block 4
@(insn 50 49 51 PR40499.c:13 (set (reg/v/f:SI 3 r3 [orig:167 arc ] [167])
@        (plus:SI (reg/v/f:SI 3 r3 [orig:167 arc ] [167])
@            (const_int 4 [0x4]))) 5 {*thumb1_addsi3} (nil))
@ 0x000c
        add     r3, r3, #4      @ 50    *thumb1_addsi3/1        [length = 2]
.L2:
        @ basic block 5
@(jump_insn 54 52 66 PR40499.c:13 (set (pc)
@        (if_then_else (ltu (reg/v/f:SI 3 r3 [orig:167 arc ] [167])
@                (reg/v/f:SI 2 r2 [orig:169 stop ] [169]))
@            (label_ref 53)
@            (pc))) 200 {*cbranchsi4_insn} (expr_list:REG_BR_PROB (const_int
9550 [0x254e])
@        (nil)))
@ 0x000e
        cmp     r3, r2  @ 54    *cbranchsi4_insn/1      [length = 4]
        bcc     .L4
        @ basic block 6
@(insn 38 66 110 PR40499.c:13 (set (reg:SI 0 r0 [orig:168 D.1218 ] [168])
@        (const_int 0 [0x0])) 168 {*thumb1_movsi_insn} (expr_list:REG_EQUAL
(const_int 0 [0x0])
@        (nil)))
@ 0x0012
        mov     r0, #0  @ 38    *thumb1_movsi_insn/2    [length = 2]
@(jump_insn 110 38 111 (set (pc)
@        (label_ref 55)) 243 {*thumb_jump} (nil))
@ 0x0014
        b       .L3     @ 110   *thumb_jump     [length = 2]
.L5:
        @ basic block 7
@(insn 39 69 55 PR40499.c:15 (set (reg:SI 0 r0 [orig:168 D.1218 ] [168])
@        (const_int 1 [0x1])) 168 {*thumb1_movsi_insn} (expr_list:REG_EQUAL
(const_int 1 [0x1])
@        (nil)))
@ 0x0016
        mov     r0, #1  @ 39    *thumb1_movsi_insn/2    [length = 2]
.L3:
        @ basic block 8
@(insn 98 97 99 PR40499.c:22 (unspec:SI [
@            (reg/f:SI 13 sp)
@        ] 6) 341 {prologue_use} (nil))
@ 0x0018
        @ sp needed for prologue        @ 98    prologue_use    [length = 4]
@(jump_insn 100 99 101 PR40499.c:22 (unspec_volatile [
@            (return)
@        ] 1) 323 {*epilogue_insns} (nil))
@ 0x001c
        bx      lr
        .size   dual_feasible, .-dual_feasible
        .ident  "GCC: (GNU) 4.5.0 20090614 (experimental) [trunk revision
148472]"



There are several interesting things going on here:

1. Note how "prologue_use" has length 4, that's probably wrong (should be
length 0?).

2. Note "epilogue_insns".  For thumb this pattern outputs instructions directly
to the cc1 output (i.e. the .s file), so these insns are never seen by
thread_prologue_and_epilogue_insns. Basically the thumb1 epilogue_insns is an
old-style text epilogue_insns instead of an RTL epilogue.


-- 

steven at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|WAITING                     |NEW
     Ever Confirmed|0                           |1
   GCC host triplet|i686-linux                  |
   Last reconfirmed|0000-00-00 00:00:00         |2009-06-20 07:23:38
               date|                            |
            Summary|[missed optimization] branch|[missed optimization] branch
                   |to return                   |to return not threaded on
                   |                            |thumb


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40499

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