Compile the attached source code with options -Os -mthumb -march=armv5te, gcc
generates:
push {r3, r4, r5, lr}
.LCFI0:
mov r4, r0
ldr r0, [r0]
bl _Z3foof
ldr r1, [r4, #4]
@ sp needed for prologue
add r5, r0, #0
bl _Z3barfi
mov r0, r5 // *
bl _Z3fffi // *
mov r4, r5 // *
mov r5, r0 // *
mov r0, r4 // *
bl _Z3fffi // *
mov r1, r0 // *
mov r0, r5 // *
bl _Z3setii
pop {r3, r4, r5, pc}
There is an obvious extra register move (mov r4, r5) in the marked section, a
better code sequence of the marked section could be:
mov r0, r5
bl _Z3fffi
mov r4, r0
mov r0, r5
bl _Z3fffi
mov r1, r0
mov r0, r4
The marked code sequence before scheduler is:
mov r4, r5
mov r0, r5
bl _Z3fffi
mov r5, r0
mov r0, r4
bl _Z3fffi
mov r1, r0
mov r0, r5
The instruction (mov r4, r5 ) is generated by register allocator. I don't know
why RA generates this instruction.
--
Summary: extra register move
Product: gcc
Version: 4.5.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40680
