Compile the attached source code with options -Os -mthumb -march=armv5te
-fno-strict-aliasing, Gcc generates:
iterate:
push {lr}
ldr r3, [r1] // C
b .L5
.L4:
ldr r3, [r3, #8] // D
.L5:
str r3, [r0] // A
ldr r3, [r0] // B
cmp r3, #0
beq .L3
ldr r2, [r3, #4]
cmp r2, #0
beq .L4
.L3:
str r3, [r0, #12]
@ sp needed for prologue
pop {pc}
Pay attention to instructions marked as A and B. Instruction A store r3 to [r0]
but insn B load it back to r3.
The instruction A was originally put after instruction C and D. After register
allocation, they were allocated to the same registers and looks exactly same.
In pass csa, cleanup_cfg was called and it found the same instructions and
moved them before instruction B. Now instruction B is obviously redundant.
Is it OK to remove this kind of redundant code in pass dce?
--
Summary: redundant memory load
Product: gcc
Version: 4.5.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40730
