------- Comment #10 from steven at gcc dot gnu dot org 2010-07-20 13:20 -------
Re. comment 9: Well, the order of *this* store and *this* load is the
difference between the test case failing or passing. So I do not think the
problem is between this load and another store.
Before sched2 (or actually, .mach on ia64):
"vector-2.c.213r.compgotos" (notes, NOPs, bundle markers removed):
;; Function f1 (f1)
30 r15:DI=r12:DI
29 r14:DI=r12:DI
35 [r15:DI++]=r32:DI
36 [post r15:DI+=0xfffffffffffffffc]=r33:DI
9 [r15:DI]=r34:SI
21 r8:DI=[r14:DI++]
28 r9:DI=[r14:DI]
18 use r8:TI
39 {return;use b0:DI;}
After .sched2:
"vector-2.c.215r.mach" (notes, NOPs, bundle markers removed):
30 r15:DI=r12:DI
29 r14:DI=r12:DI
35 [r15:DI++]=r32:DI
36 [post r15:DI+=0xfffffffffffffffc]=r33:DI
21 r8:DI=[r14:DI++]
28 r9:DI=[r14:DI]
9 [r15:DI]=r34:SI
18 use r8:TI
39 {return;use b0:DI;}
Note that the only real change in the scheduling is that insn 9 is moved after
insn 21 and insn 28. insn 9 is the store "[r15:DI]=r34:SI" that later expands
to the st4 instruction.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43494
