[Bug tree-optimization/45214] New: Poor initial RTL for bitfield operations

[bernds at gcc dot gnu dot org]

The attached testcase, from gcc's own gimplify.c, is optimized poorly at the
tree stage.  Initial RTL has

;; t_1->gsbase.plf = D.2014_8;

(insn 8 6 9 (set (reg:QI 65)
        (mem/s:QI (plus:SI (reg/v/f:SI 58 [ t ])
                (const_int 1 [0x1])) [0+1 S1 A8])) gimplify.i:48 -1
     (nil))

(insn 9 8 10 (parallel [
            (set (reg:QI 64)
                (lshiftrt:QI (reg:QI 65)
                    (const_int 3 [0x3])))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (expr_list:REG_EQUAL (lshiftrt:QI (mem/s:QI (plus:SI (reg/v/f:SI 58 [ t ])
                    (const_int 1 [0x1])) [0+1 S1 A8])
            (const_int 3 [0x3]))
        (nil)))

(insn 10 9 11 (parallel [
            (set (reg:QI 66)
                (and:QI (reg:QI 64)
                    (const_int 3 [0x3])))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (nil))

(insn 11 10 13 (parallel [
            (set (reg:QI 67)
                (ior:QI (reg:QI 66)
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (nil))

(insn 13 11 14 (parallel [
            (set (reg:QI 69)
                (and:QI (reg:QI 67)
                    (const_int 3 [0x3])))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (nil))

(insn 14 13 15 (parallel [
            (set (reg:QI 70)
                (ashift:QI (reg:QI 69)
                    (const_int 3 [0x3])))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (nil))

(insn 15 14 16 (set (reg:QI 71)
        (mem/s/j:QI (plus:SI (reg/v/f:SI 58 [ t ])
                (const_int 1 [0x1])) [0+1 S1 A8])) gimplify.i:48 -1
     (nil))

(insn 16 15 17 (parallel [
            (set (reg:QI 72)
                (and:QI (reg:QI 71)
                    (const_int -25 [0xffffffe7])))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (nil))

(insn 17 16 18 (parallel [
            (set (reg:QI 73)
                (ior:QI (reg:QI 72)
                    (reg:QI 70)))
            (clobber (reg:CC 17 flags))
        ]) gimplify.i:48 -1
     (nil))

(insn 18 17 0 (set (mem/s/j:QI (plus:SI (reg/v/f:SI 58 [ t ])
                (const_int 1 [0x1])) [0+1 S1 A8])
        (reg:QI 73)) gimplify.i:48 -1
     (nil))

This is not optimized by anything unless the combiner is extended to handle
four insns.  This PR should stay open even if the combiner is improved, until
the tree optimizers handle this better.


-- 
           Summary: Poor initial RTL for bitfield operations
           Product: gcc
           Version: 4.6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: tree-optimization
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: bernds at gcc dot gnu dot org
 GCC build triplet: i686-pc-linux-gnu
  GCC host triplet: i686-pc-linux-gnu
GCC target triplet: i686-pc-linux-gnu


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45214