http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54133
--- Comment #8 from amker.cheng <amker.cheng at gmail dot com> 2012-09-25 07:45:02 UTC --- I have spent some time investigating this bug and now I think I understand the issue. The problematic instruction patterns which save/restore argument/return registers is generated/kept on Thumb1 because ARM back end defines target hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P. The intention is to keep live range of hardware registers short, so I think it is inappropriate to do the propagation before IRA. I can only think about fixing this in following ways: 1. run an additional cprop_hardreg before register renaming. Of course this seems not decent. 2. post reload pass supports simple CSE by using cselib, we can do the transformation in postreload. Currently CSELIB can't detect such cases. Root cause is: 1. argument registers usually have no initialization; return register usually initialized by call_expr. 2. CSELIB uses the first element of the elt_list defines the mode in which the register was set; if the mode is unknown or the value is no longer valid in that mode, ELT will be NULL for the first element. 3. CSELIB creates first NULL elt_list for argument registers in function "cselib_lookup_1", because such registers has no initialization. 4. CSELIB ignores return registers initialized by call_expr, as in function "cselib_hash_rtx". Then create first NULL elt_list for return registers. 5. In function "cselib_reg_set_mode", CSELIB checks whether the first element of elt_list is NULL, this results in argument/return register won't be CSEd. But I am not sure whether CSELIB can be improved to address such issue.
