http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54850
--- Comment #5 from Pat Haugen <pthaugen at gcc dot gnu.org> 2012-10-17
23:38:16 UTC ---
I'm seeing the same thing on cpu2006 benchmark 44.namd on PowerPC64. A load is
being moved above a store to the same location, starting with revision 191493.
Reduced testcase and compile command:
[pthaugen@igoo pr54850]$ cat junk.C
// g++ -S -m64 -O2 -mcpu=power7 junk.C
class Vector {
public:
double x,y,z;
// v1 += v2;
inline void operator+=(const Vector &v2) {
x += v2.x;
y += v2.y;
z += v2.z;
}
};
Vector* foo(Vector *p, Vector *shift, Vector *p1, int n) {
int i;
for(i = 0; i < n; i++) {
p[i] = p1[i];
p[i] += *shift;
}
return p;
}
[pthaugen@igoo pr54850]$ /home/pthaugen/install/gcc/temp/bin/g++ -S -m64 -O2
-mcpu=power7 junk.C
The sched1 dump correctly lists forward dependencies of the initial store(s) to
p1[i] to the subsequent loads of p1[i], but those dependencies are gone in the
.sched2 pass.
>From .sched1 (stores are insn 75,77,79, and dependent loads are insn
80,84,88):
;; ======================================================
;; -- basic block 4 from 74 to 96 -- before reload
;; ======================================================
;; --------------- forward dependences: ------------
;; --- Region Dependences --- b 4 bb 0
;; insn code bb dep prio cost reservation
;; ---- ---- -- --- ---- ---- -----------
;; 74 379 4 0 47 2 DU_power7,LSU_power7 : 96 92
91n 87n 83n 79n 77n 75nm
;; 76 379 4 0 45 2 DU_power7,LSU_power7 : 96 92
91n 87n 83n 79n 77nm 75n
;; 78 379 4 0 45 2 DU_power7,LSU_power7 : 96 92
91n 87n 83n 79nm 77n 75n
;; 75 379 4 3 45 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 93 89n 85n 83n 81n 80n
;; 77 379 4 3 31 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 93 89n 87n 85n 84n
;; 79 379 4 3 17 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 93 91n 89n 88n
;; 80 366 4 1 39 2 DU_power7,LSU_power7 : 96 93
83n 82
;; 81 366 4 1 39 2 DU_power7,LSU_power7 : 96
91n 87n 83n 82
;; 82 740 4 2 37 6 DU_power7,VSU_power7 : 96 83
;; 83 366 4 7 31 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 93 89n 85n
;; 84 366 4 1 25 2 DU_power7,LSU_power7 : 96 93
87n 86
;; 85 366 4 3 25 2 DU_power7,LSU_power7 : 96
91n 87n 86
;; 86 740 4 2 23 6 DU_power7,VSU_power7 : 96 87
;; 87 366 4 8 17 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 93 89n
;; 88 366 4 1 11 2 DU_power7,LSU_power7 : 96 93
91n 90
>From .sched2 pass:
;; ======================================================
;; -- basic block 4 from 74 to 96 -- after reload
;; ======================================================
;; --------------- forward dependences: ------------
;; --- Region Dependences --- b 4 bb 0
;; insn code bb dep prio cost reservation
;; ---- ---- -- --- ---- ---- -----------
;; 74 379 4 0 50 2 DU_power7,LSU_power7 : 96
91n 87n 83n 92 79n 77n 75nm
;; 76 379 4 0 48 2 DU_power7,LSU_power7 : 96
91n 87n 83n 92 79n 77nm 75n
;; 78 379 4 0 48 2 DU_power7,LSU_power7 : 96
91n 87n 83n 92 79nm 77n 75n
;; 75 379 4 3 48 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 89n 85n 81n 93
;; 77 379 4 3 43 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 89n 85n 93
;; 79 379 4 3 43 6 DU_power7,(LSU_power7+FXU_power7)
: 96m 89n 93
;; 92 80 4 3 7 1 DU_power7,FXU_power7 : 96 95
;; 95 545 4 1 6 1 DU_power7,FXU_power7 : 96m
;; 93 80 4 3 43 1 DU_power7,FXU_power7 : 96 91
87 83 88 84 80
;; 81 366 4 1 42 3 DU_power7,LSU_power7 : 96
91n 87n 83n 82m
;; 80 366 4 1 42 3 DU_power7,LSU_power7 : 96
83n 88 82
;; 84 366 4 1 27 3 DU_power7,LSU_power7 : 96
87n 86
;; 82 740 4 2 39 6 DU_power7,VSU_power7 : 96 85
83 88
;; 88 366 4 3 12 3 DU_power7,LSU_power7 : 96
91n 90
