https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65979
--- Comment #19 from Oleg Endo <olegendo at gcc dot gnu.org> --- (In reply to Oleg Endo from comment #18) > Yes, that is true. However, because op0, op1, op2 are all "arith_reg_dest" > the peephole will only match if those are GP regs. Each captured insn will > only reference a single GP reg, because DImode moves should have been > smashed into SImode moves before the peephole2 pass. Thus, I think it > should be safe to just force the mode of op0 to SImode. I'll try it out. The following seems to work OK and I'd propose this as a fix for the problem: Index: gcc/config/sh/sh.md =================================================================== --- gcc/config/sh/sh.md (revision 223416) +++ gcc/config/sh/sh.md (working copy) @@ -14721,7 +14721,11 @@ || REGNO (operands[2]) == REGNO (operands[5]))" [(const_int 0)] { - sh_check_add_incdec_notes (emit_move_insn (operands[2], operands[3])); + if (REGNO (operands[1]) == REGNO (operands[2])) + operands[2] = gen_rtx_REG (SImode, REGNO (operands[0])); + + sh_check_add_incdec_notes (emit_insn (gen_rtx_SET (operands[2], + operands[3]))); emit_insn (gen_tstsi_t (operands[2], gen_rtx_REG (SImode, (REGNO (operands[1]))))); }) @@ -14748,7 +14752,8 @@ || REGNO (operands[2]) == REGNO (operands[5]))" [(const_int 0)] { - sh_check_add_incdec_notes (emit_move_insn (operands[2], operands[3])); + sh_check_add_incdec_notes (emit_insn (gen_rtx_SET (operands[2], + operands[3]))); emit_insn (gen_tstsi_t (operands[2], gen_rtx_REG (SImode, (REGNO (operands[1]))))); }) Could you guys please test this patch? Actually, now it looks quite obvious I think.