[Bug rtl-optimization/68636] unnecessary unaligned load on mips o32

[jan.sm...@alcatel-lucent.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68636

--- Comment #2 from Jan Smets <jan.sm...@alcatel-lucent.com> ---
The vreg pass is different

OLD

ode_label 16 9 17 6 2 "" [1 uses])
(note 17 16 18 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 18 17 0 6 (set (mem/v:SI (reg/f:SI 194 [ iftmp$0 ]) [2 *iftmp$0_1+0 S4
A32])
        (const_int 0 [0])) test.c:5 281 {*movsi_internal}
     (nil))


NEW

(note 17 16 18 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 18 17 19 6 (set (mem/v:BLK (reg/f:SI 194 [ D.1495 ]) [1 *_1+0 S4 A8])
        (unspec:BLK [
                (const_int 0 [0])
                (mem/v:QI (reg/f:SI 194 [ D.1495 ]) [1 *_1+0 S1 A8])
            ] UNSPEC_STORE_LEFT)) test2.c:5 276 {mov_swl}
     (nil))
(insn 19 18 0 6 (set (mem/v:BLK (reg/f:SI 194 [ D.1495 ]) [1 *_1+0 S4 A8])
        (unspec:BLK [
                (const_int 0 [0])
                (mem/v:QI (plus:SI (reg/f:SI 194 [ D.1495 ])
                        (const_int 3 [0x3])) [1 *_1+3 S1 A8])
                (mem/v:BLK (reg/f:SI 194 [ D.1495 ]) [1 *_1+0 S4 A8])
            ] UNSPEC_STORE_RIGHT)) test2.c:5 278 {mov_swr}
     (nil))


I'm not sure how to proceed from here.

Thanks