https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68862
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2015-12-15
CC| |jakub at gcc dot gnu.org,
| |uros at gcc dot gnu.org,
| |vmakarov at gcc dot gnu.org
Ever confirmed|0 |1
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r229086.
That said, I think it looks like an i386 backend problem.
I believe for pre-AVX we rely on unaligned loads/stores to be done with unspecs
(UNSPEC_LOADU/UNSPEC_STOREU and that way make sure those don't leak into
arithmetic instructions which pre-AVX can't handle unaligned memory operands.
But on this testcase those aren't used, because the load and store aren't
performed in some vector mode, but in TImode instead (as that is the mode of
the structure). So we have:
(insn 6 2 8 2 (set (reg:TI 90 [ *a_4(D) ])
(mem:TI (reg/v/f:DI 89 [ a ]) [1 *a_4(D)+0 S16 A32])) pr68862.c:15 84
{*movti_internal}
(expr_list:REG_EQUIV (mem:TI (reg/v/f:DI 89 [ a ]) [1 *a_4(D)+0 S16 A32])
(nil)))
(insn 8 6 9 2 (set (reg:V4SF 92)
(mem/u/c:V4SF (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [2 S16 A128]))
pr68862.c:17 1221 {*movv4sf_internal}
(expr_list:REG_EQUIV (const_vector:V4SF [
(const_double:SF 6.0e+0 [0x0.cp+3])
(const_double:SF 6.0e+0 [0x0.cp+3])
(const_double:SF 6.0e+0 [0x0.cp+3])
(const_double:SF 6.0e+0 [0x0.cp+3])
])
(nil)))
(insn 9 8 12 2 (set (reg:V4SF 91 [ vect__7.7 ])
(mult:V4SF (reg:V4SF 92)
(subreg:V4SF (reg:TI 90 [ *a_4(D) ]) 0))) pr68862.c:17 1436
{*mulv4sf3}
(expr_list:REG_DEAD (reg:V4SF 92)
(expr_list:REG_DEAD (reg:TI 90 [ *a_4(D) ])
(nil))))
(insn 12 9 17 2 (set (mem:TI (reg/v/f:DI 89 [ a ]) [1 *a_4(D)+0 S16 A32])
(subreg:TI (reg:V4SF 91 [ vect__7.7 ]) 0)) pr68862.c:18 84
{*movti_internal}
(expr_list:REG_DEAD (reg:V4SF 91 [ vect__7.7 ])
(expr_list:REG_DEAD (reg/v/f:DI 89 [ a ])
(nil))))
in *.ira, which is still not invalid according to the current rules, but then
LRA changes it into:
(insn 8 6 9 2 (set (reg:V4SF 21 xmm0 [92])
(mem/u/c:V4SF (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [2 S16 A128]))
pr68862.c:17 1221 {*movv4sf_internal}
(expr_list:REG_EQUIV (const_vector:V4SF [
(const_double:SF 6.0e+0 [0x0.cp+3])
(const_double:SF 6.0e+0 [0x0.cp+3])
(const_double:SF 6.0e+0 [0x0.cp+3])
(const_double:SF 6.0e+0 [0x0.cp+3])
])
(nil)))
(insn 9 8 12 2 (set (reg:V4SF 21 xmm0 [orig:91 vect__7.7 ] [91])
(mult:V4SF (reg:V4SF 21 xmm0 [92])
(mem:V4SF (reg/v/f:DI 5 di [orig:89 a ] [89]) [1 *a_4(D)+0 S16
A32]))) pr68862.c:17 1436 {*mulv4sf3}
(nil))
(insn 12 9 17 2 (set (mem:TI (reg/v/f:DI 5 di [orig:89 a ] [89]) [1 *a_4(D)+0
S16 A32])
(reg:TI 21 xmm0 [orig:91 vect__7.7 ] [91])) pr68862.c:18 84
{*movti_internal}
(nil))
Not sure what to do about this though, most of the SSE* arithmetic instructions
use nonimmediate_operand or similar predicates, we'd have to switch all of them
to use some other predicate that for pre-AVX would disallow misaligned_operand.
