https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70119
--- Comment #5 from ktkachov at gcc dot gnu.org --- Created attachment 37941 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=37941&action=edit Example patch In the interests of getting a concrete proposal out and hammering out a course of action, here's the patch I've been working on implementing my original proposal. I've restricted the subreg-and-immediate transformation in the midend to only REGs inside the AND and tweaked simplify_comparison in combine to avoid ping-ponging between the two representations. This way I only need to add a single pattern to the aarch64 backend to get the testcase to work. Where can we take this from here? 2016-03-09 Kyrylo Tkachov <kyrylo.tkac...@arm.com> PR target/70119 * combine.c (simplify_comparison): Don't looping for ever when permuting subreg and AND. * simplify-rtx.c (simplify_subreg): Move subreg into AND-reg-immediate when the mode is narrower and the immediate masks out the appropriate bits. * config/aarch64/aarch64.md (*aarch64_<optab>_reg_<mode>3_mas): New pattern. 2016-03-09 Kyrylo Tkachov <kyrylo.tkac...@arm.com> PR target/70119 * gcc.target/aarch64/var_shift_mask_1.c: New test.
