https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71389
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |ASSIGNED
Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com
--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #5)
> This looks like a dataflow infrastructure problem, not a target problem to
> me.
It is a target problem with invalid RTL sharing.
Invalid sharing is created by the code in Comment #4 when subregs are involved.
vec_extract_hi_v32qi pattern is generated in loop2_invariant pass when
misaligned V8SI move is generated, and later cprop3 pass propagates a register
to a subreg in (insn 197). The whole
(subreg:V32QI (reg:V8SI 181) 0)
RTX is shared, and the pass updates both instances of (reg:V8SI 181) to
(reg:V8SI 175) in (insn 197) and (insn 198). However, since just renamed (reg
175) doesn't trigger rescan of (insn 198) in the substitution loop, we get:
rescanning insn with uid = 197.
GLOBAL COPY-PROP: Replacing reg 181 in insn 197 with reg 175
rescanning insn with uid = 199.
GLOBAL CONST-PROP: Replacing reg 182 in insn 199 with constant (const_int 1
[0x1])
And (insn 198) isn't even recognized...
Things get downhill from this point.
The solution is to avoid invalid sharing by copying RTXes when subregs are
created, as already proposed by the patch in Comment #4.
To answer my own question: the code, referred in the second part of Comment #4
(except V4SFmode part) is processing plain REG RTXes, and these don't need
copying.
I'm testing the patch that solves the failure and possible similar problem with
V4SFmode operands:
--cut here--
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 237110)
+++ config/i386/i386.c (working copy)
@@ -19552,7 +19552,7 @@ ix86_avx256_split_vector_move_misalign (rtx op0, r
m = adjust_address (op0, mode, 0);
emit_insn (extract (m, op1, const0_rtx));
m = adjust_address (op0, mode, 16);
- emit_insn (extract (m, op1, const1_rtx));
+ emit_insn (extract (m, copy_rtx (op1), const1_rtx));
}
else
gcc_unreachable ();
@@ -19724,7 +19724,7 @@ ix86_expand_vector_move_misalign (machine_mode mod
m = adjust_address (op0, V2SFmode, 0);
emit_insn (gen_sse_storelps (m, op1));
m = adjust_address (op0, V2SFmode, 8);
- emit_insn (gen_sse_storehps (m, op1));
+ emit_insn (gen_sse_storehps (m, copy_rtx (op1)));
}
}
else
--cut here--
