https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71656
Bug ID: 71656 Summary: ICE in reload when generating code for -mcpu=power9 -mpower9-dform-vector Product: gcc Version: 7.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: bergner at gcc dot gnu.org Target Milestone: --- The following test case ICEs when generating code for POWER9 vector dform addressing and reload. It compiles fine when using LRA: bergner@genoa:~/gcc/BUGS/RELOAD$ cat bug.i typedef __attribute__((altivec(vector__))) int type_t; type_t fn1 (type_t *src) { asm volatile ("# force the base reg on the load below to be spilled" : /* no outputs */ : /* no inputs */ : "r0", "r1", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"); return src[1]; } bergner@genoa:~/gcc/BUGS/RELOAD$ /home/bergner/gcc/build/gcc-fsf-mainline-vec-dform-base/gcc/xgcc -B/home/bergner/gcc/build/gcc-fsf-mainline-vec-dform-base/gcc -S -O1 -mcpu=power9 -mpower9-dform-vector -mno-lra bug.i bug.i:1:0: warning: -mpower9-dform-vector might need -mlra typedef __attribute__((altivec(vector__))) int type_t; bug.i: In function ‘fn1’: bug.i:13:1: error: insn does not satisfy its constraints: } ^ (insn 12 7 13 2 (set (reg/i:V4SI 79 2) (mem:V4SI (plus:DI (mem/c:DI (plus:DI (reg/f:DI 113 sfp) (const_int 32 [0x20])) [2 %sfp+32 S8 A64]) (const_int 16 [0x10])) [1 MEM[(type_t *)src_2(D) + 16B]+0 S16 A128])) bug.i:13 946 {*vsx_movv4si_64bit} (nil)) bug.i:13:1: internal compiler error: in extract_constrain_insn, at recog.c:2211 The problem is that rs6000_legitimize_reload_address() does not have any support for POWER9 vector dform addresses.