https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77308
--- Comment #42 from wilco at gcc dot gnu.org --- (In reply to Bernd Edlinger from comment #40) > BTW: I found something strange in this pattern in neon.md: > > (define_insn_and_split "orndi3_neon" > [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") > (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r")) > (match_operand:DI 1 "s_register_operand" "w,r,r,0")))] Also it would be easy to support "&r,r,0" by doing op0 = ~(op0 = op2 & ~op0) so there was no need to have ARM and Thumb-2 specific alternatives...
