[Bug rtl-optimization/78590] [7 Regression] FAIL: gcc.target/aarch64/advsimd-intrinsics/vget_lane.c in change_zero_ext in combine

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78590

--- Comment #3 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Author: segher
Date: Wed Nov 30 08:24:59 2016
New Revision: 242999

URL: https://gcc.gnu.org/viewcvs?rev=242999&root=gcc&view=rev
Log:
combine: Don't mess with subregs of floating point (PR78590)

PR78590 shows a problem in change_zero_ext, where we change a zero_extend
of a subreg to a logical and.  We should only do this if the thing we are
taking the subreg of is a scalar integer, otherwise we will take a subreg
of (e.g.) a float in a different size, which is nonsensical and hits an
assert.


        PR rtl-optimization/78590
        * combine.c (change_zero_ext): Transform zero_extend of subregs only
        if the subreg_reg is a scalar integer mode.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/combine.c