https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79801
Bug ID: 79801
Summary: Disable ira.c:add_store_equivs for some targets?
Product: gcc
Version: 7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: amodra at gmail dot com
Target Milestone: ---
On powerpc, the equivalences created by add_store_equivs in ira.c seem like
they might not be very effective.
For reg1 not being assigned a hard reg, they allow lra/reload to transform the
following example sequence
(set (reg1) (mem1))
..
(set (mem2) (reg1))
..
(set (reg2) (reg1))
to
(set (mem2) (mem1))
..
(nop)
..
(set (reg2) (mem2))
PowerPC doesn't have mem-mem move insns, so of course the transformed sequence
is really
(set (rtmp) (mem1))
(set (mem2) (rtmp))
..
(nop)
..
(set (reg2) (mem2))
Net result is poor scheduling (possibly fixed by sched2). It may look like
you've reduced register pressure (reg1 has disappeared) but that is not
necessarily the case except when mem2 is a stack variable, because the lifetime
of the reg needed to load mem2 has likely been extended.
