https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79912
Palmer Dabbelt <palmer at dabbelt dot com> changed:
What |Removed |Added
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CC| |palmer at dabbelt dot com
--- Comment #12 from Palmer Dabbelt <palmer at dabbelt dot com> ---
We actually _can't_ allow integer modes in FPRs on RISC-V because it's
undefined behavior in the ISA spec (this allows flexibility in the internal
representation of FP registers, which can help the hardware). Our simulators
don't model this right now, so I'm going to go fix them, and then fix the bugs
that fall out.
If I understand this all correctly then mpf's riscv_preferred_reload_class fix
is the right way to go about it, I'm going to start running some test suites to
make sure nothing blows up.
Nobody knows why we have the f modes in movqi and friends. Andrew and I
suspect it's vestigial (probably a workaround for a bug in our port), so I'm
going to try and remove them and fix the fallout.
I believe this is a problem in the RISC-V port, so you're welcome to assign the
bug to me. I might not have time to fix this today, this way I won't lose it.
Thanks for all the info!
