https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80846
--- Comment #7 from Richard Biener <rguenth at gcc dot gnu.org> ---
Note that similar to the vec_init optab not allowing constructing larger
vectors from smaller ones vec_extract doesn't allow extracting smaller vectors
from larger ones. So I might be forced to go V8SI -> V2TI -> TI -> V4SI to
make the RTL expander happy.
In that case for AVX512 we'll expose 256bit integers into the IL which means
VRP will barf immediately and we may so anyway as if optimization somehow
exposes
a constant that won't fit in widest_int... Not sure if there's even V2OImode
supported.
For AVX2 we then expand
_6 = VIEW_CONVERT_EXPR<vector(2) uint128_t>(vect_sum_11.6_14);
_5 = BIT_FIELD_REF <_6, 128, 0>;
_29 = VIEW_CONVERT_EXPR<vector(4) int>(_5);
_22 = BIT_FIELD_REF <_6, 128, 128>;
_21 = VIEW_CONVERT_EXPR<vector(4) int>(_22);
_20 = _21 + _29;
to
;; _20 = _21 + _29;
(insn 18 17 19 (set (reg:OI 104)
(subreg:OI (reg:V2TI 89 [ _6 ]) 0)) -1
(nil))
(insn 19 18 20 (set (reg:TI 105)
(subreg:TI (reg:OI 104) 16)) -1
(nil))
(insn 20 19 21 (set (reg:OI 106)
(subreg:OI (reg:V2TI 89 [ _6 ]) 0)) -1
(nil))
(insn 21 20 22 (set (reg:TI 107)
(subreg:TI (reg:OI 106) 0)) -1
(nil))
(insn 22 21 0 (set (reg:V4SI 95 [ _20 ])
(plus:V4SI (subreg:V4SI (reg:TI 105) 0)
(subreg:V4SI (reg:TI 107) 0))) -1
(nil))
which doesn't seem any better ... (still using subregs rather than going
through vec_extract).
(define_expand "vec_extract<mode>"
[(match_operand:<ssescalarmode> 0 "register_operand")
(match_operand:VEC_EXTRACT_MODE 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_SSE"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
INTVAL (operands[2]));
DONE;
})
ssescalarmode doesn't include TImode.
Note there's the corresponding bug that says x86 doesn't implement
{ TImode, TImode } vec_init either.
