[Bug target/82106] [RISCV] Misaligned loads generated when doubles are split between stack and registers

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82106

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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           Keywords|                            |wrong-code
             Target|                            |riscv
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2017-09-06
     Ever confirmed|0                           |1