https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83009
Bug ID: 83009
Summary: [8 regression] gcc.target/aarch64/store_v2vec_lanes.c
fails with -mabi=ilp32
Product: gcc
Version: 8.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: clyon at gcc dot gnu.org
Target Milestone: ---
Hi,
As reported in https://gcc.gnu.org/ml/gcc-patches/2017-11/msg01213.html ,
the new gcc.target/aarch64/store_v2vec_lanes.c fails when using -abi=ilp32.
Kyrill said:
My patch does indeed fail to generate the optimised sequence for -mabi=ilp32.
During combine it fails to match:
Failed to match this instruction:
(set (mem:V2DF (plus:DI (reg/v/f:DI 79 [ z ])
(const_int 32 [0x20])) [1 MEM[(v2df *)z_8(D) + 32B]+0 S16 A128])
(vec_concat:V2DF (reg:DF 81 [ y0 ])
(reg:DF 84 [ y1 ])))
but without the -mabi=ilp32 it does successfully match the equivalent
(set (mem:V2DF (plus:DI (reg:DI 1 x1 [ z ])
(const_int 32 [0x20])) [1 MEM[(v2df *)z_8(D) + 32B]+0 S16 A128])
(vec_concat:V2DF (reg:DF 81 [ y0 ])
(reg:DF 84 [ y1 ])))
The only difference is the index register being the hard reg x1.
There's probably some subtlety in aarch64_classify_address that I'll need to
dig into.
