https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78821
--- Comment #27 from Uroš Bizjak <ubizjak at gmail dot com> --- (In reply to Jakub Jelinek from comment #26) > Comment on attachment 42661 [details] > Add bswaphi2 pattern > > [(set (match_operand:HI 0 "register_operand") > > Is that so that you don't have to bother with forcing operands[1] into a reg > if operands[0] is a MEM and not equal to operands[1]? Yes ;) Just a little shortcut - combine can fix this without problems nowadays. > The disadvantage of your approach is that the RA will have fewer > possibilities (for -m32 not being able to use %si/%di/%bp, and for all > arches not being able to do 16-bit bswap on memory directly (rolw $8, mem). > Guess the latter could be fixed by another peephole2, the former can't. I don't think mem/mem case is interesting, also IIRC, RA starts register allocation with regclass that has lowest number of registers to avoid spilling failures. > On the other side, it has the advantage that flags aren't clobbered from the > beginning, so perhaps sched1 or similar can do a better job. Yes, the above reason was my motivation for the proposed patch.
