https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84071
Eric Botcazou <ebotcazou at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |NEW Last reconfirmed| |2018-01-28 CC| |ebotcazou at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #3 from Eric Botcazou <ebotcazou at gcc dot gnu.org> --- > PR59461 changed nonzero_bits1 incorrectly for subregs: > > /* On many CISC machines, accessing an object in a wider mode > causes the high-order bits to become undefined. So they are > not known to be zero. */ > rtx_code extend_op; > if ((!WORD_REGISTER_OPERATIONS > /* If this is a typical RISC machine, we only have to worry > about the way loads are extended. */ > || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND > ? val_signbit_known_set_p (inner_mode, nonzero) > : extend_op != ZERO_EXTEND) > || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x)))) > && xmode_width > inner_width) > nonzero > |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK > (inner_mode)); > > If WORD_REGISTER_OPERATIONS is set and load_extend_op is ZERO_EXTEND, rtl > like > > (subreg:SI (reg:HI 125) 0) > > is assumed to be always zero-extended. That's not what the code is supposed to do. As explained in the comment, the code is intended to compute the nonzero bits of the subreg from the nonzero_bits of the inner reg: nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); > This is incorrect since modes that are smaller than WORD_MODE may contain > random top bits. This is equally true for RISC and CISC ISAs and independent > of WORD_REGISTER_OPERATIONS, so it's unclear why the !REG_P check was added. No, that's wrong, WORD_REGISTER_OPERATIONS precisely means that the bits up to the word are defined when operations operate in mode smaller than a word.