Bug ID: 84343
           Summary: Behavior of ARM register constraint 't' seems to be
                    inconsistent with documentation
           Product: gcc
           Version: 8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: inline-asm
          Assignee: unassigned at gcc dot
          Reporter: pablo.barrio at arm dot com
  Target Milestone: ---

Not sure if I am misunderstanding something here. The following code with
inline assembly:

typedef double Bar_t;
Bar_t bar(Bar_t a, Bar_t b) {
  Bar_t res;
    __asm__ ("vadd.F32 %0, %1, %2": "=t" (res) : "t" (a), "t" (b));
    return res;

generates the following assembly:

vadd.F32 s0, s0, s2

In order to make it use double registers, I am using operand identifier 'P' in
%0, %1, %2. Then, the instruction gets allocated to d0 & d1 instead of s0 & s2.
If I use a 128-bit vector datatype, I can also make the code select q registers
by using operand modifier 'q'.

The GNU documentation states the following:

ARM family—config/arm/
        VFP floating-point registers s0-s31. Used for 32 bit values.

First, should the "Used for 32 bit values" be dropped, since it can also be
used for 64-bit values (and for vectors with lanes of different values)?

Second, the fact that it mentions s0-s31 misled me a bit and I initially
thought that it *only* allowed 32-bit values. Would it be possible to mention
that this constraint is really selecting the lower vector registers, i.e.
s0-s31, d0-d15 or q0-q7, which I believe is what is really happening? I can't
think of a proper way to write this though.

I haven't added a preprocessed file here since I don't think there is a bug in
the source code.

Many thanks

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