--- Comment #4 from Timothy Pearson <tpearson at raptorengineering dot com> ---
(In reply to Andrew Pinski from comment #3)
> This is 100% the equivalent code.
> jmp     *(%r15) # opline.199_67->handler
> Does two things:
> loads a pointer from %r15 and then jumps to that pointer.
> In PowerPC, you can only jump indirectly via the CTR or LR registers.
>         ld 9,0(29)       # opline.200_67->handler, gotovar.1505_2678
>         mtctr 9  # gotovar.1505_2678, gotovar.1505_2678
>         bctr
> Most likely what is happening is the indirect branch predictor is not
> predicting the branch correctly on the powerpc side while it is on the x86
> side.  This is a micro-architecture difference between the two chips and is
> unrelated to the ISA differences.

I'm forwarding this for analysis to see if there's anything we can do in
firmware to "fix" the branch predictor.  If not, is there a way to prime the
predictor in this scenario, or is this too specific to be added compiler-side?

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