https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86014
Bug ID: 86014
Summary: [AArch64] missed LDP optimization
Product: gcc
Version: 9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: clyon at gcc dot gnu.org
Target Milestone: ---
After r260952 (Improve LDP/STP generation that requires a base register),
I noticed that the new test ldp_stp_10.c fails in ILP32 mode:
FAIL: gcc.target/aarch64/ldp_stp_10.c scan-assembler-times
ldp\tw[0-9]+, w[0-9]+, 2
FAIL: gcc.target/aarch64/ldp_stp_10.c scan-assembler-times
ldp\tx[0-9]+, x[0-9]+, 2
Kyrill thinks it's a missed-optimization:
This is because the register allocation is such that the last load in the
sequence clobbers the address register like so:
...
ldr w0, [x2, 1600]
ldr w1, [x2, 2108]
ldr w3, [x2, 1604]
ldr w2, [x2, 2112] //<<--- x2 is an address and a destination
...
The checks in aarch64_operands_adjust_ok_for_ldpstp bail out for this case.
I believe as long as w2 is loaded in the second/last LDP pair that this
optimisation generates
and the address is not a writeback address (as we are guaranteed in this
context) then it should
be safe to form the LDP pairs.
