https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87836
--- Comment #8 from Eric Botcazou <ebotcazou at gcc dot gnu.org> --- > That's the immediate cause of the ICE. I haven't identified the root cause > yet. I'm wondering, though, why the compiler built and ran on x86 hardware, > but failed on SPARC hardware. One difference is that the configuration on > SPARC hardware uses the native assembler. On x86 hardware, it uses the GNU > assembler. That's the only configuration difference. One possibility is that the base compiler miscompiles the stage #1 compiler. In order to rule it out, we need to make sure that the base compiler is invoked with optimization disabled, hence my request about the flags...
