https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87485
--- Comment #16 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #15)
> (In reply to Uroš Bizjak from comment #14)
> > (In reply to Jakub Jelinek from comment #13)
> > > (In reply to Uroš Bizjak from comment #12)
> > > > (In reply to Jakub Jelinek from comment #10)
> > > > > and r264676 fixed that ICE, but hangs on it.
> > > > Are you sure you have correct revision here? Mentioned revision removes
> > > > FPSR
> > > > x87 status register, which x86_64 should not use at all. The description
> > > > mentions r264726 that mentions many changes in ira-lives.c and
> > > > lra-lives.c
> > >
> > > Yes.
> >
> > Strange... Even more strange is the fact, that it works for me with:
> >
> > GCC: (GNU) 9.0.0 20181119 (experimental) [trunk revision 266278]
> >
> > $ /ssd/uros/gcc-build/gcc/cc1 -quiet -O2 -fschedule-insns
> > -fno-guess-branch-probability -fno-isolate-erroneous-paths-dereference
> > -fno-omit-frame-pointer -fno-split-wide-types -fno-tree-ccp -fno-tree-sra
> > pr87485.c; echo $?
> > pr87485.c: In function ‘c8’:
> > pr87485.c:19:23: warning: division by zero [-Wdiv-by-zero]
> > 19 | *xh += fl < (e4 / 0);
> > | ^
> > 0
>
> Ah, needs also -fstack-protector-strong.
The compiler goes into reload loop, the loop can be seen in _reload dump, which
will quickly grow to several megabytes:
Choosing alt 0 in insn 60: (0) =a (1) =&d (2) 0 (3) rm
{*udivmodsi4_zext_1}
Creating newreg=146, assigning class AREG to r146
60:
{r146:DI=zero_extend(udiv(r146:DI#0,r119:SI));r118:SI=umod(r146:DI#0,r119:SI);clobber
flags:CC;}
REG_DEAD r119:SI
REG_DEAD r116:SI
REG_UNUSED r118:SI
REG_UNUSED flags:CC
Inserting insn reload before:
146: clobber r146:DI
147: r146:DI#0=r116:SI
Inserting insn reload after:
148: r125:TI#0=r146:DI
...
Choosing alt 0 in insn 60: (0) =a (1) =&d (2) 0 (3) rm
{*udivmodsi4_zext_1}
Creating newreg=149 from oldreg=146, assigning class AREG to r149
60:
{r149:DI=zero_extend(udiv(r149:DI#0,r119:SI));r118:SI=umod(r149:DI#0,r119:SI);clobber
flags:CC;}
REG_DEAD r119:SI
REG_UNUSED r118:SI
REG_UNUSED flags:CC
Inserting insn reload before:
151: clobber r149:DI
152: r149:DI#0=r146:DI#0
Inserting insn reload after:
153: r146:DI=r149:DI
...
Choosing alt 0 in insn 60: (0) =a (1) =&d (2) 0 (3) rm
{*udivmodsi4_zext_1}
Creating newreg=151 from oldreg=149, assigning class AREG to r151
60:
{r151:DI=zero_extend(udiv(r151:DI#0,r119:SI));r118:SI=umod(r151:DI#0,r119:SI);clobber
flags:CC;}
REG_DEAD r119:SI
REG_UNUSED r118:SI
REG_UNUSED flags:CC
Inserting insn reload before:
156: clobber r151:DI
157: r151:DI#0=r149:DI#0
Inserting insn reload after:
158: r149:DI=r151:DI
...
