--- Comment #2 from Segher Boessenkool <segher at gcc dot> ---
Thanks for the analysis!

(In reply to Vladimir Makarov from comment #1)
> The very first ira-costs pass runs in sched1 and it generates the following
> costs
>   r125 costs: BASE_REGS:10000 GENERAL_REGS:10000 LINK_REGS:20000

> Why does IRA calculate such costs?  We have 2 insns involving p125
>    15: r125:DI=%3:DI
>              REG_DEAD %3:DI
>     7: {r123:SI=asm_operands/*r125 with constraint 'v'*/;clobber ca:SI;}
> Cost of moving r3 into p125 is 2 for base regs and 4 for memory
> Cost of moving p125 into a v reg is 8 for base regs and 4 for memory

Ah, so we we need to improve that.

This is power8, where mtvsr insns are still a bit expensive, but not more
expensive than memory.

> Therefore cost of p125 is 10 for base reg and 8 for memory (multiplied by BB
> frequency 10000).
> Therefore IRA chooses memory for p125.
> In this particular case insn 15 can go away when we assign r3 to p125.  It
> means the cost for base reg could be 8 as for memory but IRA can not say in
> general case that it can assign r3 to p125.
> I think increasing memory move cost at least to 5 could solve the problem. 
> But probably it needs benchmarking SPEC, besides running GCC testsuite, to
> see that the performance is not worse after such change.


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