https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89570
--- Comment #12 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to rsand...@gcc.gnu.org from comment #6)
> (2) not splitting out the condition in a (vec_)cond_expr if it
> isn't supported as a stand-alone operation
(2) can be just documented as a requirement, unless we have targets that would
need further changes. So, if IFN_COND_* is supported for certain modes, then
vec_cmp{,u} needs to be supported for that mode too. I bet masked operations
are done using those bitmasks that are set by vec_cmp{,u}, dunno how exactly
for aarch64, but if x86 is adjusted to use those, it would be the mask
registers and
all the arithmetic etc. vector instructions masked.
