https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> --- We do that if mfence isn't supported: /* For seq-cst stores, when we lack MFENCE, use XCHG. */ if (is_mm_seq_cst (model) && !(TARGET_64BIT || TARGET_SSE2)) { emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode), operands[0], operands[1], operands[2])); DONE; } /* Otherwise use a store. */ emit_insn (gen_atomic_store<mode>_1 (operands[0], operands[1], operands[2])); } /* ... followed by an MFENCE, if required. */ if (is_mm_seq_cst (model)) emit_insn (gen_mem_thread_fence (operands[2])); So, I guess we need to benchmark both and if xchg is beneficial on some CPUs, use it there guarded by some tuning flag.