https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95285
--- Comment #9 from Wilco <wilco at gcc dot gnu.org> --- (In reply to Bu Le from comment #7) > (In reply to Wilco from comment #5) > > (In reply to Bu Le from comment #0) > > > > Also it would be much more efficient to have a relocation like this if you > > wanted a 48-bit PC-relative offset: > > > > adrp x0, bar1.2782 > > add x0, x0, :lo12:bar1.2782 > > movk x0, :high32_47:bar1.2782 > > I am afraid that put the PC-relative offset into x0 is not correct, because > x0 issuppose to be the final address of bar1 rather than an PC offset. > Therefore an extra register is needed to hold the offest temporarily. You're right, we need an extra add, so it's like this: adrp x0, bar1.2782 movk x1, :high32_47:bar1.2782 add x0, x0, x1 add x0, x0, :lo12:bar1.2782 > (By the way, the high32_47 relocation you suggested is the prel_g2 in the > officail aarch64 ABI released) It needs a new relocation because of the ADRP. ADR could be used so the existing R_<CLS>_MOVW_PREL_G0-3 work, but then you need 5 instructions. > And in terms of engineering, you idea can save the trouble to modify the > linker for calculating the offset for 3 movks. But we still need to make a > new relocation type for ADRP, because it currently checking the overflow of > address and gives the "relocation truncated to fit" error. Therefore, both > idea need to do works in binutils, which make it also equivalent. There is relocation 276 (R_<CLS>_ADR_PREL_PG_HI21_NC).
