[Bug tree-optimization/97579] [11 Regression] ICE in gimple_expand_vec_cond_expr, at gimple-isel.cc:201 since r11-4123-g128f43cf679e5156

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97579

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |rguenth at gcc dot 
gnu.org
             Status|NEW                         |ASSIGNED

--- Comment #9 from Richard Biener <rguenth at gcc dot gnu.org> ---
mask__258.181_254 = vect_cst__77 != { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 };
mask__581.199_1001 = VEC_COND_EXPR <mask__258.181_254, { 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0 }, mask__649.185_117>;

so we're having a VEC_COND_EXPR with vector boolean type, sth we are not
prepared to handle (at least if it's not a classical vector mode one).

          if (used_vec_cond_exprs >= 2
              && (get_vcond_mask_icode (mode, TYPE_MODE (op0_type))
                  != CODE_FOR_nothing)
              && expand_vec_cmp_expr_p (op0a_type, op0_type, tcode))
            {
              /* Keep the SSA name and use vcond_mask.  */
              tcode = TREE_CODE (op0);
            }

in the implicit else we assume vcond can handle this, but it will obviously
fail for a non-vector mode.

  icode = get_vcond_icode (mode, cmp_op_mode, unsignedp);

where we have mode == HImode and cmp_op_mode V16SImode.  I'm not sure aarch64
SVE or riscv will like VNBImode here.

Unless we want to disallow vector boolean typed VEC_COND_EXPRs alltogether
we have to lower them somewhere which probably is in ISEL.  For the above
we'd produce

  _75 = ~mask__258.181_254;
  _897 = mask__649.185_117 & _75;
  mask__581.199_1001 = _897;