https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102169
--- Comment #2 from Peter Bergner <bergner at gcc dot gnu.org> ---
So we have the following during IRA:
(insn 7 2 8 2 (set (reg:SI 120 [ barD.3297 ])
(mem/c:SI (plus:DI (unspec:DI [
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
(reg:DI 2 2)
] UNSPEC_TOCREL)
(const_int 4 [0x4])) [1 barD.3297+0 S4 A32])) "bug.i":5:13 544
{*movsi_internal1}
(expr_list:REG_EQUIV (mem/c:SI (plus:DI (unspec:DI [
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
(reg:DI 2 2)
] UNSPEC_TOCREL)
(const_int 4 [0x4])) [1 barD.3297+0 S4 A32])
(nil)))
(insn 8 7 11 2 (set (mem/c:SI (unspec:DI [
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
(reg:DI 2 2)
] UNSPEC_TOCREL) [1 fooD.3296+0 S4 A32])
(reg:SI 120 [ barD.3297 ])) "bug.i":5:13 544 {*movsi_internal1}
(expr_list:REG_DEAD (reg:SI 120 [ barD.3297 ])
(nil)))
...with:
Pass 1 for finding pseudo/allocno costs
r120: preferred GEN_OR_VSX_REGS, alternative NO_REGS, allocno
GEN_OR_VSX_REGS
a0(r120,l0) costs: BASE_REGS:0,0 GENERAL_REGS:0,0 FLOAT_REGS:0,0
ALTIVEC_REGS:0,0 VSX_REGS:4000,4000 GEN_OR_FLOAT_REGS:8000,8000
GEN_OR_VSX_REGS:8000,8000 LINK_REGS:12000,12000 CTR_REGS:12000,12000
LINK_OR_CTR_REGS:12000,12000 SPEC_OR_GEN_REGS:12000,12000 ALL_
REGS:36000,36000 MEM:8000,8000
[snip]
Allocno a0r120 of GEN_OR_VSX_REGS(93) has 93 avail. regs 0 3-12 14-95,
node: 0 3-12 14-95 (confl regs = 1-2 13 96-110)
[snip]
Pushing a0(r120,l0)(cost 0)
Popping a0(r120,l0) -- assign reg 32
Disposition:
0:r120 l0 32
Looking at REG_ALLOC_ORDER, f32 is the first register we attempt to use and
since it has the same zero cost as the GPRs, we end up keeping it.
