https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106342
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |iii at gcc dot gnu.org,
| |jakub at gcc dot gnu.org,
| |krebbel at gcc dot gnu.org
--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think the problem is in the
r11-3816-ga1a10a0b8c4e161070f88de3af9d20f9f866a23f
change. The "copysign<mode>3" expander in config/s390/vector.md uses VFT
iterator, I assume if_then_else form it was using has intructions covering all
those modes, but after the change it attempts to match the "vsel<mode>" pattern
from config/s390/vx-builtins.md, which uses just the V_HW iterator.
VFT is V1DF V2DF without TARGET_VXE and V1SF V2SF V4SF V1DF V2DF V1TF TF with
TARGET_VXE, while V_HW is V16QI V8HI V4SI V2DI V2DF without TARGET_VXE and
V16QI V8HI V4SI V2DI V1TI V2DF V4SF V1TF TF with TARGET_VXE.
So, for V1SF V2SF V1DF modes copysign pattern will expand to something that
will not match an actual pattern.
So, either "copysign<mode>3" expander in config/s390/vector.md should use VF_HW
iterator instead of VFT (and thus not support V1SF, V2SF and V1DF modes), or
because presumably vsel doesn't raise exceptions, it could just use a wider
mode for those cases.
Thus, either:
--- gcc/config/s390/vector.md.jj 2022-01-11 23:11:21.985295845 +0100
+++ gcc/config/s390/vector.md 2022-07-28 17:39:19.968033927 +0200
@@ -1723,12 +1723,12 @@
; Vector copysign, implement using vector select
(define_expand "copysign<mode>3"
- [(set (match_operand:VFT 0 "register_operand" "")
- (ior:VFT
- (and:VFT (match_operand:VFT 2 "register_operand" "")
- (match_dup 3))
- (and:VFT (not:VFT (match_dup 3))
- (match_operand:VFT 1 "register_operand" ""))))]
+ [(set (match_operand:VF_HW 0 "register_operand" "")
+ (ior:VF_HW
+ (and:VF_HW (match_operand:VF_HW 2 "register_operand" "")
+ (match_dup 3))
+ (and:VF_HW (not:VF_HW (match_dup 3))
+ (match_operand:VF_HW 1 "register_operand" ""))))]
"TARGET_VX"
{
rtx mask = s390_build_signbit_mask (<MODE>mode);
or perhaps something like:
--- gcc/config/s390/vector.md.jj 2022-01-11 23:11:21.985295845 +0100
+++ gcc/config/s390/vector.md 2022-07-28 19:02:06.527108712 +0200
@@ -1721,6 +1721,13 @@
operands[4] = CONST0_RTX (V2DImode);
})
+(define_mode_attr hw_vec[(V1SF "V4SF") (V2SF "V4SF") (V4SF "V4SF")
+ (V1DF "V2DF") (V2DF "V2DF")
+ (V1TF "V1TF") (TF "TF")])
+(define_mode_attr hw_vec_l[(V1SF "v4sf") (V2SF "v4sf") (V4SF "v4sf")
+ (V1DF "v2df") (V2DF "v2df")
+ (V1TF "v1tf") (TF "tf")])
+
; Vector copysign, implement using vector select
(define_expand "copysign<mode>3"
[(set (match_operand:VFT 0 "register_operand" "")
@@ -1731,6 +1738,20 @@
(match_operand:VFT 1 "register_operand" ""))))]
"TARGET_VX"
{
+ if (GET_MODE_SIZE (<MODE>mode) < 16)
+ {
+ rtx op0 = gen_reg_rtx (<hw_vec>mode), op1, op2;
+ op1 = simplify_gen_subreg (<hw_vec>mode,
+ force_reg (<MODE>mode, operands[1]),
+ <MODE>mode, 0);
+ op2 = simplify_gen_subreg (<hw_vec>mode,
+ force_reg (<MODE>mode, operands[2]),
+ <MODE>mode, 0);
+ emit_insn (gen_copysign<hw_vec_l>3 (op0, op1, op2));
+ emit_move_insn (operands[0],
+ simplify_gen_subreg (<MODE>mode, op0, <hw_vec>mode, 0));
+ DONE;
+ }
rtx mask = s390_build_signbit_mask (<MODE>mode);
operands[3] = force_reg (<MODE>mode, mask);
})
(dunno whether to use simplify_gen_subreg or lowpart_subreg or
simplify_gen_subreg with 8).
