https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107674
Bug ID: 107674
Summary: [11/12/13 Regressions] arm: MVE codegen regressions on
VCTP and vector LDR/STR instructions
Product: gcc
Version: 12.2.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: stammark at gcc dot gnu.org
Target Milestone: ---
We've found a couple of performance regressions with Arm MVE. These can be
seen here:
https://godbolt.org/z/onPjfW4zj
* Between GCC 11 and 12 we seem to have started emitting a strange
vmrs/sxth/vmsr instruction sequence after the vctp instruction. I suspect this
is something to do with the introduction of MODE_VECTOR_BOOL during that
period.
* Between GCC 12 and 13 we are no longer merging the pointer increments by #16
into the ldr/strs and we have some random movs that aren't needed either. This
also happened in GCC 11, but we want to keep the improved codegen of GCC 12
here ;)
This looks like a change in register allocation:
Choosing alt 0 in insn 24: (0) =w (1) Ux (2) Up {mve_vldrhq_z_sv8hi}
Creating newreg=149, assigning class CORE_REGS to INC/DEC result r149
Creating newreg=150 from oldreg=134, assigning class VPR_REG to r150
bad vs good
Choosing alt 0 in insn 24: (0) =w (1) Ux (2) Up {mve_vldrhq_z_sv8hi}
Creating newreg=149 from oldreg=134, assigning class VPR_REG to r149
Does anyone have any further ideas on why these may have changed or how to fix
them?
Thanks!
