[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Actually this is aarch64:
        ldr     x1, [x0, #:lo12:.LANCHOR0]
        ldr     w0, [x3, 8]
        and     w0, w2, w0, lsr 6
        add     x0, x0, 200
        ldr     w0, [x1, x0, lsl 2]
        str     w0, [x1, 800]

Note I need to better understand why the C++ front-end thinks this would be
invalid ...