https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092
Bug ID: 109092
Summary: [13 Regression] ICE: RTL check: expected code 'reg',
have 'subreg' in rhs_regno, at rtl.h:1932 when
building libgcc on riscv64
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Keywords: build, ice-on-valid-code
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: zsojka at seznam dot cz
Target Milestone: ---
Host: x86_64-pc-linux-gnu
Target: riscv64-unknown-linux-gnu
$ cat testcase.c
void foo(int i) {}
$ /repo/build-gcc-trunk-riscv64/./gcc/cc1 -mabi=lp64d -march=rv64imafdc
testcase.c -quiet
during RTL pass: vregs
testcase.c: In function 'foo':
testcase.c:1:18: internal compiler error: RTL check: expected code 'reg', have
'subreg' in rhs_regno, at rtl.h:1932
1 | void foo(int i) {}
| ^
0x7a0e7d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
/repo/gcc-trunk/gcc/rtl.cc:916
0x93b82e rhs_regno(rtx_def const*)
/repo/gcc-trunk/gcc/rtl.h:1932
0x958236 rhs_regno(rtx_def const*)
/repo/gcc-trunk/gcc/config/riscv/pic.md:87
0x958236 recog_17
/repo/gcc-trunk/gcc/config/riscv/riscv.md:1750
0x1ac76aa recog_174
/repo/gcc-trunk/gcc/config/riscv/vector-iterators.md:326
0xb527dc recog_memoized(rtx_insn*)
/repo/gcc-trunk/gcc/recog.h:273
0xfdff84 extract_insn(rtx_insn*)
/repo/gcc-trunk/gcc/recog.cc:2789
0xd111ff instantiate_virtual_regs_in_insn
/repo/gcc-trunk/gcc/function.cc:1611
0xd111ff instantiate_virtual_regs
/repo/gcc-trunk/gcc/function.cc:1985
0xd111ff execute
/repo/gcc-trunk/gcc/function.cc:2034
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Currently build with RTL checking enabled for the riscv64-unknown-linux-gnu
target fails.
