[Bug target/89835] The RISC-V target uses amoswap.w for relaxed stores

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89835

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Patrick O'Neill <pone...@gcc.gnu.org>:

https://gcc.gnu.org/g:6a2383f47ae70c31f91775142b9fb03f697741c2

commit r14-403-g6a2383f47ae70c31f91775142b9fb03f697741c2
Author: Patrick O'Neill <patr...@rivosinc.com>
Date:   Wed Apr 5 09:56:33 2023 -0700

    RISC-V: Strengthen atomic stores

    This change makes atomic stores strictly stronger than table A.6 of the
    ISA manual. This mapping makes the overall patchset compatible with
    table A.7 as well.

    2023-04-27 Patrick O'Neill <patr...@rivosinc.com>

            PR target/89835

    gcc/ChangeLog:

            * config/riscv/sync.md (atomic_store<mode>): Use simple store
            instruction in combination with fence(s).

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/pr89835.c: New test.

    Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>