https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573
--- Comment #4 from Luke Geeson <luke.geeson at cs dot ucl.ac.uk> ---
Ah so since atomics are treated as volatile (like LLVM) instructions that
access them cannot inhabit a delay slot. Is it still valid to treat atomics as
volatile?
Consider the following MIPS litmus test:
```
{ %x0=x; %y0=y; %y1=y; %x1=x; }
P0 | P1 ;
lw $2,0(%x0) | lw $2,0(%y1) ;
ori $3,$0,1 | ori $3,$0,1 ;
sw $3,0(%y0) | sw $3,0(%x1) ;
exists (0:$2=1 /\ 1:$2=1)
```
When run under the mips model we do not observe the outcome in the exists
clause:
```
0:$2=0; 1:$2=0;
0:$2=0; 1:$2=1;
0:$2=1; 1:$2=0;
```
That is, from an ordering perspective it is unlikely that unexpected behaviours
can occur - in this case putting sw in a delay slot should be ok (the same
doesn't hold for RISC-V/Arm models of course).
I understand treating atomics as volatile has historical precedent but a case
can be made, at least on modern architectures and with improved understanding
of models, that atomics are not volatile and more optimisations can be applied.
What do you think?
