[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Kewen Lin <li...@gcc.gnu.org>:

https://gcc.gnu.org/g:e58899645f09fb26fbca03ed8b9b13f162ff32dc

commit r12-9795-ge58899645f09fb26fbca03ed8b9b13f162ff32dc
Author: Kewen Lin <li...@linux.ibm.com>
Date:   Wed Jul 26 03:42:29 2023 -0500

    rs6000: Correct vsx operands output for xxeval [PR110741]

    PR110741 exposes one issue that we didn't use the correct
    character for vsx operands in output operand substitution,
    consequently it can map to the wrong registers which hold
    some unexpected values.

            PR target/110741

    gcc/ChangeLog:

            * config/rs6000/vsx.md (define_insn xxeval): Correct vsx
            operands output with "x".

    gcc/testsuite/ChangeLog:

            * g++.target/powerpc/pr110741.C: New test.

    (cherry picked from commit 96a839233ced3a0bfc3d5492a6d8b102e6981472)