https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111119
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
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CC| |crazylht at gmail dot com
--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Richard Biener from comment #0)
> We have
>
> (define_expand "maskload<mode><sseintvecmodelower>"
> [(set (match_operand:V48_AVX2 0 "register_operand")
> (unspec:V48_AVX2
> [(match_operand:<sseintvecmode> 2 "register_operand")
> (match_operand:V48_AVX2 1 "memory_operand")]
> UNSPEC_MASKMOV))]
> "TARGET_AVX")
>
> and
>
> (define_mode_iterator V48_AVX2
> [V4SF V2DF
> V8SF V4DF
> (V4SI "TARGET_AVX2") (V2DI "TARGET_AVX2")
> (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")])
>
> so for example maskloadv4siv4si is disabled with just -mavx while the actual
> instruction can operate just fine on SImode sized data by pretending its
> SFmode.
>
> check_effective_target_vect_masked_load is conditional on AVX, not AVX2.
>
> With just AVX we can still use SSE2 vectorization for integer operations
> using
> masked loads/stores from AVX.
I see, we can add an alternative like "noavx2,avx2" to generate vmaskmovps/pd
when avx2 is not available for integer.
