https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111870
Bug ID: 111870
Summary: Miscompile of atomic rmw or on x86 (not aarch, though)
Product: gcc
Version: 13.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: fallenleafs at icloud dot com
Target Milestone: ---
Recently I wrote one little piece of code that gave me too much headache. After
investigation, I discovered that on x86 the sequence of instructions that GCC
(strangely, llvm as well) produces is invalid because after applying
optimisations, atomicity of load gets elided. You can witness that gcc makes up
nonsense here[https://godbolt.org/z/Thfeq1KGW]. There you can find c code and
if you compile it with gcc13.2 to aarch, atomic_fetch_or_explicit gets
translated to a loop of a pair of special load-store instructions which is
correct lowering, but if you do it for x86, you can, in fact, witness that
generated code does not contain `lock or ...` instruction, which would be
correct code, but instead `lock cmpxchg ...` which is invalid.
