https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90693

--- Comment #6 from Wilco <wilco at gcc dot gnu.org> ---
Thanks Jakub - with the 2nd patch we get the expected sequence on AArch64:

        sub     x1, x0, #1
        eor     x0, x0, x1
        cmp     x0, x1
        cset    x0, hi

Reply via email to