[Bug target/112445] [14 Regression] ICE: in lra_split_hard_reg_for, at lra-assigns.cc:1861 unable to find a register to spill: {*umulditi3_1} with -O -march=cascadelake -fwrapv since r14-4968-g89e5d902fc55ad

[jakub at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112445

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Just changing
--- i386.md.xx  2023-11-22 09:47:22.746637132 +0100
+++ i386.md     2023-11-22 20:38:07.216218697 +0100
@@ -9984,7 +9984,7 @@
   [(set (match_operand:<DWI> 0 "register_operand" "=r,A")
        (mult:<DWI>
          (zero_extend:<DWI>
-           (match_operand:DWIH 1 "register_operand" "%d,a"))
+           (match_operand:DWIH 1 "register_operand" "%d,0"))
          (zero_extend:<DWI>
            (match_operand:DWIH 2 "nonimmediate_operand" "rm,rm"))))
    (clobber (reg:CC FLAGS_REG))]
makes the testcase pass.  A question is how RA treats 0 constraint when the two
operands have different modes, if it is basically the same as a in that case,
meaning that the first input operand will never be in %rdx even when the A
constraint contains %rax and %rdx registers (but the double-word mode implies
it must be low part in %rax high part in $rdx).