[Bug target/111720] RISC-V: Ugly codegen in RVV

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111720

--- Comment #30 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:990769a343f090088f5025ad233f88824b2c6263

commit r14-5769-g990769a343f090088f5025ad233f88824b2c6263
Author: Pan Li <pan2...@intel.com>
Date:   Mon Nov 13 11:22:37 2023 +0800

    DSE: Allow vector type for get_stored_val when read < store

    Update in v4:
    * Merge upstream and removed some independent changes.

    Update in v3:
    * Take known_le instead of known_lt for vector size.
    * Return NULL_RTX when gap is not equal 0 and not constant.

    Update in v2:
    * Move vector type support to get_stored_val.

    Original log:

    This patch would like to allow the vector mode in the
    get_stored_val in the DSE. It is valid for the read
    rtx if and only if the read bitsize is less than the
    stored bitsize.

    Given below example code with
    --param=riscv-autovec-preference=fixed-vlmax.

    vuint8m1_t test () {
      uint8_t arr[32] = {
        1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9,
        1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9,
      };

      return __riscv_vle8_v_u8m1(arr, 32);
    }

    Before this patch:
    test:
      lui     a5,%hi(.LANCHOR0)
      addi    sp,sp,-32
      addi    a5,a5,%lo(.LANCHOR0)
      li      a3,32
      vl2re64.v       v2,0(a5)
      vsetvli zero,a3,e8,m1,ta,ma
      vs2r.v  v2,0(sp)             <== Unnecessary store to stack
      vle8.v  v1,0(sp)             <== Ditto
      vs1r.v  v1,0(a0)
      addi    sp,sp,32
      jr      ra

    After this patch:
    test:
      lui     a5,%hi(.LANCHOR0)
      addi    a5,a5,%lo(.LANCHOR0)
      li      a4,32
      addi    sp,sp,-32
      vsetvli zero,a4,e8,m1,ta,ma
      vle8.v  v1,0(a5)
      vs1r.v  v1,0(a0)
      addi    sp,sp,32
      jr      ra

    Below tests are passed within this patch:
    * The risc-v regression test.
    * The x86 bootstrap and regression test.
    * The aarch64 regression test.

            PR target/111720

    gcc/ChangeLog:

            * dse.cc (get_stored_val): Allow vector mode if read size is
            less than or equal to stored size.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr111720-0.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-1.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-10.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-2.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-3.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-4.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-5.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-6.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-7.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-8.c: New test.
            * gcc.target/riscv/rvv/base/pr111720-9.c: New test.

    Signed-off-by: Pan Li <pan2...@intel.com>